After integrated circuits are formed on a semiconductor wafer, the top metal layer is defined as a plurality of bonding pads to form a multi-layered wiring with the metal lines below. The wafer is then cut into dies for further IC chip electronic packaging.
In the electronic packaging of an IC chip, the dies cut from the wafer are bonded to a lead frame with a bonder, and the bonding pads on the IC chip are electrically connected with corresponding electrical leads on the lead frame by wire bonding. In other words, the bonding pads on IC chips are the interface between the integrated circuits on the semiconductor substrate and the packaging leads on the lead frame to connect electrical signals. The electrical signals can be power signals, ground signals, and/or input/output signals.
Conventionally, the active devices, e.g., MOS transistors or resistances, are laid on the central area (active area) of an IC chip and bonding pads are disposed around the active area to protect the active devices on the active area from damage during wire bonding. In some cases, bonding pads are laid on the central area of IC chip and active devices are disposed around the bonding pads for the same reason.
The conventional shape of a bonding pad is a square or a rectangle. FIG. 1 shows a conventional die array on a wafer. There are scribe lines 16 on a wafer 10 to define several die areas, e.g. 12A and 12B, and the wafer 10 is cut into dies along the scribe lines 16. There are alignment markers (e.g. 14A˜14C) disposed at corners of the die areas 12A and 12B on the scribe lines 16 for cutting alignment. For the intact die area 12A, the dicing machine cuts the die area 12A from the wafer 10 by aligning with the markers 14A and 14B which are disposed along the diagonal line of area 12A. However, for the fragmental die area 12B, there is no corresponding diagonal markers on scribe lines for alignment, and therefore, there is difficulty cutting die area 12B.
FIGS. 2A and 2B show a conventional design of bonding pads. In FIG. 2A, the rectangular bonding pads 22A with equal size are disposed along the two longer sides of the rectangular chip 20A which is cut from a wafer. Another bonding pad design is shown in FIG. 2B. The rectangular bonding pads 22B with equal size are disposed on the central area of the rectangular chip 20B which is also cut from a wafer. The electrical layout in the chip 20A or 20B is predetermined and the bonding pads 22A or 22B on the IC chip 20A or 20B respectively are wire bonded with corresponding electrical leads on a lead frame according to the interior layout. However, it is hard to identify the bonding orientation of a chip and the leads on a lead frame because the IC chips 20A and 20B are rectangular and the bonding pads 22A and 22B are disposed on the IC chips 20A and 20B symmetrically.
The same orientation problem occurs on probe pads. The probe pads are disposed in certain positions on a circuit for in-line monitoring or checking the electrical performance of the circuit design. FIG. 3 shows the conventional design for probe pads. There are several tiny probe pads 36 disposed in a certain circuit 34 on IC chip 30. The inspector measures the probe pads 36 on the circuit 34 by using a micro-probe under a microscope to obtain the electrical data.
Since the square-shaped probe pads on the circuit are very tiny (e.g., 5×5 μm), it is hard and time consuming for an inspector to identify the layout orientation between the probe pads 36 on the circuit 34 under a microscope.